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| Da ta S h e e t , V 3 .0 , J a n . 2 0 0 1 C161CS-32R/-L C161JC-32R/-L C161JI-32R/-L 16-Bit Single-Chip Microcontroller Microcontrollers Never stop thinking. Edition 2001-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Da ta S h e e t , V 3 .0 , J a n . 2 0 0 1 C161CS-32R/-L C161JC-32R/-L C161JI-32R/-L 16-Bit Single-Chip Microcontroller Microcontrollers Never stop thinking. C161CS/JC/JI Revision History: Previous Version: Page All 2 27, 28 29 35 39ff 51 53 57 60 62 63 65ff 1) 2001-01 2000-08 V2.0 (intermediate version) 1999-03 (Advance Information) V3.0 Subjects (major changes since last revision)1) Converted to Infineon layout Derivative Synopsis Table updated GPT block diagrams updated RTC description improved OWD description improved RSTCON and SDLM registers added Description of input/output voltage and hysteresis improved Separate table for power consumption Clock generation mode table updated External clock drive specification improved Reset calibration time specified, definition of VAREF improved Programmable sample time introduced Timing tables updated to 25 MHz 4, 6, 10, 18 Programmable Interface Routing introduced Changes refer to version 1999-03. Controller Area Network (CAN): License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com 16-Bit Single-Chip Microcontroller C166 Family C161CS/JC/JI C161CS/JC/JI * High Performance 16-bit CPU with 4-Stage Pipeline - 80 ns Instruction Cycle Time at 25 MHz CPU Clock - 400 ns Multiplication (16 x 16 bit), 800 ns Division (32 / 16 bit) - Enhanced Boolean Bit Manipulation Facilities - Additional Instructions to Support HLL and Operating Systems - Register-Based Design with Multiple Variable Register Banks - Single-Cycle Context Switching Support - 16 MBytes Total Linear Address Space for Code and Data - 1024 Bytes On-Chip Special Function Register Area * 16-Priority-Level Interrupt System with 59 Sources, Sample-Rate down to 40 ns * 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC) * Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input - Additional 32 kHz Oscillator * On-Chip Memory Modules - 2 KBytes On-Chip Internal RAM (IRAM) - 8 KBytes On-Chip Extension RAM (XRAM) - 256 KBytes On-Chip Mask ROM * On-Chip Peripheral Modules - 12-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 s - Two 16-Channel Capture/Compare Units (eight IO lines each) - Two Multi-Functional General Purpose Timer Units with 5 Timers - Two Asynchronous/Synchronous Serial Channels - High-Speed Synchronous Serial Channel (SPI) - On-Chip CAN Interface (Rev. 2.0B active, Full CAN / Basic CAN) with 15 Message Objects (C161CS 2x, C161JC 1x) - Serial Data Link Module (SDLM), compliant with J1850, supporting Class 2 (C161JC/JI) - IIC Bus Interface (10-bit Addressing, 400 kHz) with 2 Channels (multiplexed) - On-Chip Real Time Clock * Up to 16 MBytes External Address Space for Code and Data - Programmable External Bus Characteristics for Different Address Ranges - Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width - Five Programmable Chip-Select Signals - Hold- and Hold-Acknowledge Bus Arbitration Support Data Sheet 1 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L * Idle, Sleep, and Power Down Modes with Flexible Power Management * Programmable Watchdog Timer and Oscillator Watchdog * Up to 93 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis * Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards * On-Chip Bootstrap Loader * 128-Pin TQFP Package This document describes several derivatives of the C161 group. Table 1 enumerates these derivatives and summarizes the differences. As this document refers to all of these derivatives, some descriptions may not apply to a specific product. Table 1 Derivative SAK-C161CS-32RF SAB-C161CS-32RF SAK-C161CS-LF SAB-C161CS-LF SAK-C161JC-32RF SAB-C161JC-32RF SAK-C161JC-LF SAB-C161JC-LF SAK-C161JI-32RF SAB-C161JI-32RF SAK-C161JI-LF SAB-C161JI-LF C161CS/JC/JI Derivative Synopsis On-Chip Program Memory 256 KByte ROM --256 KByte ROM --256 KByte ROM --Serial Bus Interface(s) CAN1, CAN2 CAN1, CAN2 CAN1, SDLM CAN1, SDLM SDLM SDLM Maximum CPU Frequency 25 MHz 25 MHz 25 MHz 25 MHz 25 MHz 25 MHz For simplicity all versions are referred to by the term C161CS/JC/JI throughout this document. Data Sheet 2 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: * the derivative itself, i.e. its function set, the temperature range, and the supply voltage * the package and the type of delivery. For the available ordering codes for the C161CS/JC/JI please refer to the "Product Catalog Microcontrollers", which summarizes all available microcontroller variants. Note: The ordering codes for Mask-ROM versions are defined for each product after verification of the respective ROM code. Introduction The C161CS/JC/JI derivatives are high performance derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. They combine high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM, internal RAM, and extension RAM. VAREF VAGND VDD VSS XTAL1 XTAL2 XTAL3 XTAL4 RSTIN RSTOUT NMI EA READY ALE RD WR/WRL Port 5 12 Bit Port 0 16 Bit Port 1 16 Bit Port 2 8 Bit Port 3 15 Bit C161CS/JC/JI Port 4 8 Bit Port 6 8 Bit Port 7 4 Bit Port 9 6 Bit MCL04450 Figure 1 Data Sheet Logic Symbol 3 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Pin Configuration (top view) P1H.7/A15/CC27IO P1H.6/A14/CC26IO P1H.5/A13/CC25IO P1H.4/A12/CC24IO P1H.3/A11 P1H.2/A10 P1H.1/A9 P1H.0/A8 RSTIN XTAL4 XTAL3 RSTOUT NMI VSS VDD P6.0/CS0 P6.1/CS1 P6.2/CS2 P6.3/CS3 P6.4/CS4 P6.5/HOLD P6.6/HLDA P6.7/BREQ P7.4/CC28IO/* P7.5/CC29IO/* P7.6/CC30IO/* P7.7/CC31IO/* VSS VDD P9.0/SDA0 P9.1/SCL0 P9.2/SDA1 P9.3/SCL1 P9.4/SDA2 P9.5 VSS VDD P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 P1L.7/A7 P1L.6/A6 P1L.5/A5 P1L.4/A4 P1L.3/A3 P1L.2/A2 P1L.1/A1 P1L.0/A0 P0H.7/AD15 P0H.6/AD14 P0H.5/AD13 P0H.4/AD12 P0H.3/AD11 P0H.2/AD10 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 XTAL1 XTAL2 VSS VDD VSS VDD VSS P0H.1/AD9 P0H.0/AD8 VSS VDD P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2/AD2 P0L.1/AD1 P0L.0/AD0 EA ALE READY WR/WRL RD C161CS/JC/JI VSS VDD P4.7/A23/* P4.6/A22/* P4.5/A21/* P4.4/A20/* P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 VSS VDD P3.15/CLKOUT/FOUT P3.13/SCLK P3.12/BHE/WRH VAREF VAGND VSS VDD VSS VDD P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4EUD P5.15/AN15/T2EUD P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IO/EX2IN P2.11/CC11IO/EX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7INT7IN P3.0/T0IN/TxD1 P3.1/T6OUT/RxD1 P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TxD0 P3.11/RxD0 P5.6/AN6 P5.7/AN7 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 MCP04451 Figure 2 *) The marked pins of Port 4 and Port 7 can have interface lines assigned to them (CAN interface in the C161CS and C161JC, SDLM interface in the C161JC and C161JI). Table 2 on the pages below lists the possible assignments. Data Sheet 4 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 2 Symbol Pin No. RST OUT 1 Pin Definitions and Functions Input Outp. O Function Internal Reset Indication Output. This pin is set to a low level when the part is executing either a hardware-, a software- or a watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. When the PWRDN (power down) instruction is executed, the NMI pin must be low in order to force the C161CS/JC/JI to go into power down mode. If NMI is high, when PWRDN is executed, the part will continue to run in normal mode. If not used, pin NMI should be pulled high externally. Port 6 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 6 outputs can be configured as push/ pull or open drain drivers. The Port 6 pins also serve for alternate functions: Chip Select 0 Output CS0 Chip Select 1 Output CS1 Chip Select 2 Output CS2 Chip Select 3 Output CS3 Chip Select 4 Output CS4 External Master Hold Request Input HOLD Hold Acknowledge Output (master mode) HLDA or Input (slave mode) Bus Request Output BREQ NMI 2 I P6 IO P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 5 6 7 8 9 10 11 12 O O O O O I I/O O Data Sheet 5 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 2 Symbol Pin No. P7 Pin Definitions and Functions (cont'd) Input Outp. IO Function Port 7 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 7 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 7 is selectable (TTL or special). Port 7 pins provide inputs/ outputs for CAPCOM2 and serial interface lines.1) CC28IO CAPCOM2: CC28 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input, (C161CS/JC) CAN2_RxD CAN 2 Receive Data Input, (C161CS) SDL_TxD SDLM Transmit Data Output (C161JC/JI) CC29IO CAPCOM2: CC29 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output, (C161CS/JC) CAN2_TxD CAN 2 Transmit Data Output, (C161CS) SDL_RxD SDLM Receive Data Input (C161JC/JI) CC30IO CAPCOM2: CC30 Capture Inp./Compare Outp., CAN1_RxD CAN 1 Receive Data Input, (C161CS/JC) CAN2_RxD CAN 2 Receive Data Input, (C161CS) SDL_TxD SDLM Transmit Data Output (C161JC/JI) CC31IO CAPCOM2: CC31 Capture Inp./Compare Outp., CAN1_TxD CAN 1 Transmit Data Output, (C161CS/JC) CAN2_TxD CAN 2 Transmit Data Output, (C161CS) SDL_RxD SDLM Receive Data Input (C161JC/JI) Port 9 is a 6-bit bidirectional open drain I/O port (provide external pullup resistors if required). It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The following Port 9 pins also serve for alternate functions: SDA0 IIC Bus Data Line 0 SCL0 IIC Bus Clock Line 0 SDA1 IIC Bus Data Line 1 SCL1 IIC Bus Clock Line 1 SDA2 IIC Bus Data Line 2 - P7.4 13 P7.5 14 P7.6 15 P7.7 16 I/O I I O I/O O O I I/O I I O I/O O O I IO P9 P9.0 P9.1 P9.2 P9.3 P9.4 P9.5 19 20 21 22 23 24 I/O I/O I/O I/O I/O - Note: Port 9 pins can only tolerate positive overload currents (see Table 9). Data Sheet 6 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 2 Symbol Pin No. P5 Pin Definitions and Functions (cont'd) Input Outp. I Function Port 5 is a 12-bit input-only port with Schmitt-Trigger char. The pins of Port 5 also serve as analog input channels for the A/D converter, or they serve as timer inputs: AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN12, T6IN GPT2 Timer T6 Count Inp. AN13, T5IN GPT2 Timer T5 Count Inp. AN14, T4EUD GPT1 Timer T4 Ext. Up/Down Ctrl. Inp. AN15, T2EUD GPT1 Timer T5 Ext. Up/Down Ctrl. Inp. P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.12 P5.13 P5.14 P5.15 27 28 29 30 31 32 33 34 37 38 39 40 I I I I I I I I I I I I Data Sheet 7 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 2 Symbol Pin No. P2 Pin Definitions and Functions (cont'd) Input Outp. IO Function Port 2 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 2 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins also serve for alternate functions: CC8IO CAPCOM1: CC8 Capture Inp./Compare Output, EX0IN Fast External Interrupt 0 Input CC9IO CAPCOM1: CC9 Capture Inp./Compare Output, EX1IN Fast External Interrupt 1 Input CC10IO CAPCOM1: CC10 Capture Inp./Compare Outp., EX2IN Fast External Interrupt 2 Input CC11IO CAPCOM1: CC11 Capture Inp./Compare Outp., EX3IN Fast External Interrupt 3 Input CC12IO CAPCOM1: CC12 Capture Inp./Compare Outp., EX4IN Fast External Interrupt 4 Input CC13IO CAPCOM1: CC13 Capture Inp./Compare Outp., EX5IN Fast External Interrupt 5 Input CC14IO CAPCOM1: CC14 Capture Inp./Compare Outp., EX6IN Fast External Interrupt 6 Input CC15IO CAPCOM1: CC15 Capture Inp./Compare Outp., EX7IN Fast External Interrupt 7 Input, T7IN CAPCOM2: Timer T7 Count Input P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15 43 44 45 46 47 48 49 50 I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I Note: During Sleep Mode a spike filter on the EXnIN interrupt inputs suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. Data Sheet 8 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 2 Symbol Pin No. P3 Pin Definitions and Functions (cont'd) Input Outp. IO Function Port 3 is a 15-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The input threshold of Port 3 is selectable (TTL or special). The following Port 3 pins also serve for alternate functions: T0IN CAPCOM1 Timer T0 Count Input, TxD1 ASC1 Clock/Data Output (Async./Sync) T6OUT GPT2 Timer T6 Toggle Latch Output, RxD1 ASC1 Data Input (Async.) or Inp./Output (Sync.) CAPIN GPT2 Register CAPREL Capture Input T3OUT GPT1 Timer T3 Toggle Latch Output T3EUD GPT1 Timer T3 External Up/Down Control Input T4IN GPT1 Timer T4 Count/Gate/Reload/Capture Inp T3IN GPT1 Timer T3 Count/Gate Input T2IN GPT1 Timer T2 Count/Gate/Reload/Capture Inp MRST SSC Master-Receive/Slave-Transmit Inp./Outp. MTSR SSC Master-Transmit/Slave-Receive Outp./Inp. TxD0 ASC0 Clock/Data Output (Async./Sync.) RxD0 ASC0 Data Input (Async.) or Inp./Outp. (Sync.) External Memory High Byte Enable Signal, BHE External Memory High Byte Write Strobe WRH SCLK SSC Master Clock Output / Slave Clock Input. CLKOUT System Clock Output (= CPU Clock) FOUT Programmable Frequency Output P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.15 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 I O O I/O I O I I I I I/O I/O O I/O O O I/O O O Data Sheet 9 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 2 Symbol Pin No. P4 Pin Definitions and Functions (cont'd) Input Outp. IO Function Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. The Port 4 outputs can be configured as push/pull or open drain drivers. The input threshold of Port 4 is selectable (TTL or special). Port 4 can be used to output the segment address lines and for serial interface lines:1) A16 Least Significant Segment Address Line A17 Segment Address Line A18 Segment Address Line A19 Segment Address Line A20 Segment Address Line, CAN2_RxD CAN 2 Receive Data Input, (C161CS) SDL_RxD SDLM Receive Data Input (C161JC/JI) A21 Segment Address Line, CAN1_RxD CAN 1 Receive Data Input, (C161CS/JC) A22 Segment Address Line, CAN1_TxD CAN 1 Transmit Data Output, (C161CS/JC) CAN2_TxD CAN 2 Transmit Data Output, (C161CS) SDL_RxD SDLM Receive Data Input (C161JC/JI) A23 Most Significant Segment Address Line, CAN1_RxD CAN 1 Receive Data Input, (C161CS/JC) CAN2_TxD CAN 2 Transmit Data Output, (C161CS) CAN2_RxD CAN 2 Receive Data Input, (C161CS) SDL_TxD SDLM Transmit Data Output (C161JC/JI) External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode this pin is activated for every external data write access. In WRL-mode this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in register SYSCON for mode selection. P4.0 P4.1 P4.2 P4.3 P4.4 70 71 72 73 74 P4.5 P4.6 75 76 P4.7 77 O O O O O I I O I O O O I O I O I O O O RD WR/ WRL 80 81 Data Sheet 10 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 2 Symbol Pin No. READY 82 Pin Definitions and Functions (cont'd) Input Outp. I Function Ready Input. When the Ready function is enabled, a high level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to a low level. An internal pullup device will hold this pin high when nothing is driving it. Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. A low level at this pin during and after Reset forces the C161CS/JC/JI to begin instruction execution out of external memory. A high level forces execution out of the internal program memory. "ROMless" versions must have this pin tied to `0'. PORT0 consists of the two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: D0 - D7 D0 - D7 P0H.0 - P0H.7: I/O D8 - D15 Multiplexed bus modes: Data Path Width: 8-bit 16-bit P0L.0 - P0L.7: AD0 - AD7 AD0 - AD7 P0H.0 - P0H.7: A8 - A15 AD8 - AD15 ALE 83 O EA 84 I PORT0 P0L.0-7 8592 P0H.0-7 95102 IO Note: At the end of an external reset (EA = `0') PORT0 also inputs the configuration values. Data Sheet 11 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 2 Symbol Pin No. PORT1 P1L.0-7 103110 P1H.0-7 113120 Pin Definitions and Functions (cont'd) Input Outp. IO Function PORT1 consists of the two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. PORT1 is used as the 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: CC24IO CAPCOM2: CC24 Capture Inp./Compare Outp. CC25IO CAPCOM2: CC25 Capture Inp./Compare Outp. CC26IO CAPCOM2: CC26 Capture Inp./Compare Outp. CC27IO CAPCOM2: CC27 Capture Inp./Compare Outp. XTAL2: XTAL1: Output of the oscillator amplifier circuit. Input to the oscillator amplifier and input to the internal clock generator To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Input to the 32-kHz oscillator amplifier and input to the internal clock generator XTAL4: Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL3, while leaving XTAL4 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. XTAL3: P1H.4 P1H.5 P1H.6 P1H.7 XTAL2 XTAL1 117 118 119 120 123 124 I/O I/O I/O I/O O I XTAL3 XTAL4 126 127 I O Data Sheet 12 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 2 Symbol Pin No. RSTIN 128 Pin Definitions and Functions (cont'd) Input Outp. I/O Function Reset Input with Schmitt-Trigger characteristics. A low level at this pin while the oscillator is running resets the C161CS/ JC/JI. An internal pullup resistor permits power-on reset using only a capacitor connected to VSS. A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 ns + 2 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT). See note below this table. Note: To let the reset configuration of PORT0 settle and to let the PLL lock a reset duration of ca. 1 ms is recommended. VAREF VAGND VDD 35 36 - - Reference voltage for the A/D converter. Reference ground for the A/D converter. Digital Supply Voltage: +5 V during normal operation and idle mode. 2.5 V during power down mode if RTC is off 2.7 V during power down mode if RTC is running 4, 18, - 262), 42, 52, 68, 78, 93, 111, 121 3, 17, - 252), 41, 51, 69, 79, 94, 112, 122, 125 VSS Digital Ground. 1) The CAN and/or SDLM interface lines are assigned to ports P4 and P7 under software control. Within the CAN module or SDLM several assignments can be selected. Supply pins 25 and 26 feed the Analog/Digital Converter and should be decoupled separately. 2) Data Sheet 13 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Note: The following behavioural differences must be observed when the bidirectional reset is active: * Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. * The reset indication flags always indicate a long hardware reset. * The PORT0 configuration is treated as if it were a hardware reset. In particular, the bootstrap loader may be activated when P0L.4 is low. * Pin RSTIN may only be connected to external reset devices with an open drain output driver. * A short hardware reset is extended to the duration of the internal reset sequence. Data Sheet 14 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Functional Description The architecture of the C161CS/JC/JI combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the C161CS/JC/JI. Note: All time specifications refer to a CPU clock of 25 MHz (see definition in the AC Characteristics section). Data Dual Port ProgMem ROM 256 KByte 32 Instr. / Data C166-Core 16 IRAM Internal RAM 2 KByte CPU 16 Data 16 XRAM 8 KByte External Instr. / Data Osc / PLL PEC XTAL ASC1 (USART) On-Chip XBUS (16-Bit Demux) Interrupt Controller 16-Level Priority 16 Interrupt Bus 16 Peripheral Data Bus RTC WDT IIC 400 KBd, 2 Ch. CAN/SDLM 2.0B act. / Cl.B ADC 10-Bit 12 Channels ASC0 (USART) SSC (SPI) GPT T2 T3 T4 T5 CCOM2 CCOM1 T7 T8 T0 T1 Port 4 8 EBC XBUS Control External Bus Control Port 0 16 Port 1 16 Port 6 8 BRGen Port 5 12 BRGen Port 3 15 T6 Port 7 4 Port 9 6 MCB04323_1CSR Figure 3 Block Diagram The program memory, the internal RAM (IRAM) and the set of generic peripherals are connected to the CPU via separate buses. A fourth bus, the XBUS, connects external resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3). The XBUS resources (XRAM, CAN, SDLM, IIC, ASC1) of the C161CS/JC/JI can be enabled during initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). If the X-Peripherals remain disabled they consume neither address space nor port pins. Data Sheet 15 V3.0, 2001-01 Port 2 8 C161CS/JC/JI-32R C161CS/JC/JI-L Memory Organization The memory space of the C161CS/JC/JI is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bitaddressable. The C161CS/JC/JI incorporates 256 KBytes of on-chip mask-programmable ROM for code or constant data. The lower 32 KBytes of the on-chip ROM can be mapped either to segment 0 or segment 1. 2 KBytes of on-chip Internal RAM (IRAM) are provided as a storage for user defined variables, for the system stack, general purpose register banks and even for code. A register bank can consist of up to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, ..., RL7, RH7) so-called General Purpose Registers (GPRs). 1024 bytes (2 x 512 bytes) of the address space are reserved for the Special Function Register areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for future members of the C166 Family. 8 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks, or code. The XRAM is accessed like external memory and therefore cannot be used for the system stack or for register banks and is not bitaddressable. The XRAM permits 16-bit accesses with maximum speed. In order to meet the needs of designs where more memory is required than is provided on chip, up to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller. Data Sheet 16 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required, or to one of four different external memory access modes, which are as follows: - - - - 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed In the demultiplexed bus modes, addresses are output on PORT1 and data is input/ output on PORT0 or P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user the adaption of a wide range of different types of memories and external peripherals. In addition, up to 4 independent address windows may be defined (via register pairs ADDRSELx / BUSCONx) which control the access to different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 and BUSCON2 overrides BUSCON1. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated in order to save external glue logic. The C161CS/JC/JI offers the possibility to switch the CS outputs to an unlatched mode. In this mode the internal filter logic is switched off and the CS signals are directly generated from the address. The unlatched CS mode is enabled by setting CSCFG (SYSCON.6). Access to very slow memories or memories with varying access times is supported via a particular `Ready' function. A HOLD/HLDA protocol is available for bus arbitration and allows to share external resources with other bus masters. The bus arbitration is enabled by setting bit HLDEN in register PSW. After setting HLDEN once, pins P6.7 ... P6.5 (BREQ, HLDA, HOLD) are automatically controlled by the EBC. In Master Mode (default after reset) the HLDA pin is an output. By setting bit DP6.7 to `1' the Slave Mode is selected where pin HLDA is switched to input. This allows to directly connect the slave controller to another master controller without glue logic. For applications which require less than 16 MBytes of external memory space, this address space can be restricted to 1 MByte, 256 KByte, or to 64 KByte. In this case Port 4 outputs four, two, or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used. Data Sheet 17 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Note: When one or both of the on-chip CAN Modules or the SDLM are used with the interface lines assigned to Port 4, the interface lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 ... A16. CS lines can be used to increase the total amount of addressable external memory. Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Based on these hardware provisions, most of the C161CS/JC/JI's instructions can be executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For example, shift and rotate instructions are always processed during one machine cycle independent of the number of bits to be shifted. All multiple-cycle instructions have been optimized so that they can be executed very fast as well: branches in 2 cycles, a 16 x 16 bit multiplication in 5 cycles and a 32-/16-bit division in 10 cycles. Another pipeline optimization, the so-called `Jump Cache', allows reducing the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle. CPU SP STKOV STKUN Exec. Unit Instr. Ptr. Instr. Reg. 32 ROM 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Page Ptr. MDH MDL Mul/Div-HW Bit-Mask Gen ALU (16-bit) Barrel - Shifter Context Ptr. ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. R0 Registers 16 Internal RAM R15 General Purpose R15 R0 16 MCB02147 Figure 4 Data Sheet CPU Block Diagram 18 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L The CPU has a register context consisting of up to 16 wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU at any time. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, a register bank may overlap others. A system stack of up to 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack pointer value upon each stack access for the detection of a stack overflow or underflow. The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly efficient C161CS/JC/JI instruction set which includes the following instruction classes: - - - - - - - - - - - - Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words. A variety of direct, indirect or immediate addressing modes are provided to specify the required operands. Data Sheet 19 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Interrupt System With an interrupt response time within a range from just 5 to 12 CPU clocks (in case of internal program execution), the C161CS/JC/JI is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of the C161CS/JC/JI supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller. Any of these interrupt requests can be programmed to being serviced by the Interrupt Controller or by the Peripheral Event Controller (PEC). In contrast to a standard interrupt service where the current program execution is suspended and a branch to the interrupt vector table is performed, just one cycle is `stolen' from the current CPU activity to perform a PEC service. A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is implicity decremented for each PEC service except when performing in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source related vector location. PEC services are very well suited, for example, for supporting the transmission or reception of blocks of data. The C161CS/JC/JI has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For the standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. Table 3 shows all of the possible C161CS/JC/JI interrupt sources and the corresponding hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers. Note: Interrupt nodes which are not used by associated peripherals, may be used to generate software controlled interrupt requests by setting the respective interrupt request bit (xIR). Data Sheet 20 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 3 C161CS/JC/JI Interrupt Nodes Enable Flag CC0IE CC1IE CC2IE CC3IE CC4IE CC5IE CC6IE CC7IE CC8IE CC9IE CC10IE CC11IE CC12IE CC13IE CC14IE CC15IE CC16IE CC17IE CC18IE CC19IE CC20IE CC21IE CC22IE CC23IE CC24IE CC25IE CC26IE CC27IE CC28IE CC29IE 21 Source of Interrupt or Request PEC Service Request Flag CAPCOM Register 0 CAPCOM Register 1 CAPCOM Register 2 CAPCOM Register 3 CAPCOM Register 4 CAPCOM Register 5 CAPCOM Register 6 CAPCOM Register 7 CAPCOM Register 8 CAPCOM Register 9 CAPCOM Register 10 CAPCOM Register 11 CAPCOM Register 12 CAPCOM Register 13 CAPCOM Register 14 CAPCOM Register 15 CAPCOM Register 16 CAPCOM Register 17 CAPCOM Register 18 CAPCOM Register 19 CAPCOM Register 20 CAPCOM Register 21 CAPCOM Register 22 CAPCOM Register 23 CAPCOM Register 24 CAPCOM Register 25 CAPCOM Register 26 CAPCOM Register 27 CAPCOM Register 28 CAPCOM Register 29 Data Sheet Interrupt Vector CC0INT CC1INT CC2INT CC3INT CC4INT CC5INT CC6INT CC7INT CC8INT CC9INT CC10INT CC11INT CC12INT CC13INT CC14INT CC15INT CC16INT CC17INT CC18INT CC19INT CC20INT CC21INT CC22INT CC23INT CC24INT CC25INT CC26INT CC27INT CC28INT CC29INT Vector Location 00'0040H 00'0044H 00'0048H 00'004CH 00'0050H 00'0054H 00'0058H 00'005CH 00'0060H 00'0064H 00'0068H 00'006CH 00'0070H 00'0074H 00'0078H 00'007CH 00'00C0H 00'00C4H 00'00C8H 00'00CCH 00'00D0H 00'00D4H 00'00D8H 00'00DCH 00'00E0H 00'00E4H 00'00E8H 00'00ECH 00'00E0H 00'0110H Trap Number 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 44H V3.0, 2001-01 CC0IR CC1IR CC2IR CC3IR CC4IR CC5IR CC6IR CC7IR CC8IR CC9IR CC10IR CC11IR CC12IR CC13IR CC14IR CC15IR CC16IR CC17IR CC18IR CC19IR CC20IR CC21IR CC22IR CC23IR CC24IR CC25IR CC26IR CC27IR CC28IR CC29IR C161CS/JC/JI-32R C161CS/JC/JI-L Table 3 C161CS/JC/JI Interrupt Nodes (cont'd) Enable Flag CC30IE CC31IE T0IE T1IE T7IE T8IE T2IE T3IE T4IE T5IE T6IE CRIE ADCIE ADEIE S0TIE S0TBIE S0RIE S0EIE SCTIE SCRIE SCEIE XP0IE XP1IE XP2IE XP3IE XP4IE XP5IE XP6IE XP7IE Interrupt Vector CC30INT CC31INT T0INT T1INT T7INT T8INT T2INT T3INT T4INT T5INT T6INT CRINT ADCINT ADEINT S0TINT S0TBINT S0RINT S0EINT SCTINT SCRINT SCEINT XP0INT XP1INT XP2INT XP3INT XP4INT XP5INT XP6INT XP7INT Vector Location 00'0114H 00'0118H 00'0080H 00'0084H 00'00F4H 00'00F8H 00'0088H 00'008CH 00'0090H 00'0094H 00'0098H 00'009CH 00'00A0H 00'00A4H 00'00A8H 00'011CH 00'00ACH 00'00B0H 00'00B4H 00'00B8H 00'00BCH 00'0100H 00'0104H 00'0108H 00'010CH 00'0120H 00'0124H 00'0128H 00'012CH Trap Number 45H 46H 20H 21H 3DH 3EH 22H 23H 24H 25H 26H 27H 28H 29H 2AH 47H 2BH 2CH 2DH 2EH 2FH 40H 41H 42H 43H 48H 49H 4AH 4BH Source of Interrupt or Request PEC Service Request Flag CAPCOM Register 30 CAPCOM Register 31 CAPCOM Timer 0 CAPCOM Timer 1 CAPCOM Timer 7 CAPCOM Timer 8 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Reg. A/D Overrun Error ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error SSC Transmit SSC Receive SSC Error IIC Protocol Event CAN1 (C161CS/JC) PLL/OWD and RTC ASC1 Transmit ASC1 Receive ASC1 Error CAN2 (C161CS) or SDLM (C161JC/JI) Data Sheet CC30IR CC31IR T0IR T1IR T7IR T8IR T2IR T3IR T4IR T5IR T6IR CRIR ADEIR S0TIR S0TBIR S0RIR S0EIR SCTIR SCRIR SCEIR XP1IR XP2IR XP3IR XP4IR XP5IR XP6IR XP7IR A/D Conversion Compl. ADCIR IIC Data Transfer Event XP0IR 22 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L The C161CS/JC/JI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called `Hardware Traps'. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to a dedicated vector table location). The occurence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Table 4 shows all of the possible exceptions or error conditions that can arise during runtime: Table 4 Hardware Trap Summary Trap Flag - RESET RESET RESET 00'0000H 00'0000H 00'0000H 00H 00H 00H 02H 04H 06H 0AH 0AH 0AH 0AH 0AH III III III II II II I I I I I Trap Vector Vector Location Trap Number Trap Priority Exception Condition Reset Functions: Hardware Reset Software Reset W-dog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt NMI Stack Overflow STKOF Stack Underflow STKUF Class B Hardware Traps: Undefined Opcode Protected Instruction Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Reserved Software Traps TRAP Instruction NMITRAP 00'0008H STOTRAP 00'0010H STUTRAP 00'0018H 00'0028H 00'0028H 00'0028H 00'0028H 00'0028H UNDOPC BTRAP PRTFLT BTRAP ILLOPA ILLINA ILLBUS BTRAP BTRAP BTRAP - - - - [2CH - 3CH] [0BH - 0FH] - Current CPU Priority Any Any [00'0000H - [00H - 00'01FCH] 7FH] in steps of 4H Data Sheet 23 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Capture/Compare (CAPCOM) Units The CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 16 TCL. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation (PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external events. Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the capture/compare register array. The input clock for the timers is programmable to several prescaled values of the internal system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7 allow event scheduling for the capture/ compare registers relative to external events. Both of the two capture/compare register arrays contain 16 dual purpose capture/ compare registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8, respectively), and programmed for capture or compare function. Eight registers of each module have one port pin associated with it which serves as an input pin for triggering the capture function, or as an output pin to indicate the occurrence of a compare event. When a capture/compare register has been selected for capture mode, the current contents of the allocated timer will be latched (`captured') into the capture/compare register in response to an external event at the port pin which is associated with this register. In addition, a specific interrupt request for this capture/compare register is generated. Either a positive, a negative, or both a positive and a negative external signal transition at the pin can be selected as the triggering event. The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers. Table 5 Mode 0 Mode 1 Mode 2 Mode 3 Compare Modes (CAPCOM) Function Interrupt-only compare mode; several compare interrupts per timer period are possible Pin toggles on each compare match; several compare events per timer period are possible Interrupt-only compare mode; only one compare interrupt per timer period is generated Pin set `1' on match; pin reset `0' on compare time overflow; only one compare event per timer period is generated 24 V3.0, 2001-01 Compare Modes Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L When a match occurs between the timer value and the value in a capture/compare register, specific actions will be taken based on the selected compare mode. Reload Reg. TxREL fCPU TxIN GPT2 Timer T6 Over/Underflow CCxIO 2n : 1 Tx Input Control CAPCOM Timer Tx Interrupt Request 8 Capture Inputs 8 Compare Outputs Mode Control (Capture or Compare) 16-Bit Capture/ Compare Registers 16 Capture/Compare Interrupt Request CCxIO fCPU GPT2 Timer T6 Over/Underflow 2n : 1 Ty Input Control CAPCOM Timer Ty Interrupt Request x = 0, 7 y = 1, 8 n = 3 ... 10 Figure 5 Reload Reg. TyREL MCB02143c CAPCOM Unit Block Diagram Data Sheet 25 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of four basic modes of operation, which are Timer, Gated Timer, Counter, and Incremental Interface Mode. In Timer Mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while Counter Mode allows a timer to be clocked in reference to external events. Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the timers in module GPT1 is 16 TCL. The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD) to facilitate e.g. position tracking. In Incremental Interface Mode the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B via their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals, so the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has an output toggle latch (T3OTL) which changes its state on each timer overflow/underflow. The state of this latch may be output on pin T3OUT e.g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. Data Sheet 26 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L T2EUD fCPU T2IN 2n : 1 T2 Mode Control U/D GPT1 Timer T2 Interrupt Request (T2IR) Reload Capture Interrupt Request (T3IR) T3 Mode Control Toggle FF GPT1 Timer T3 U/D T3OTL T3OUT fCPU 2n : 1 T3IN T3EUD Capture Reload T4IN fCPU T4EUD 2n : 1 T4 Mode Control GPT1 Timer T4 U/D Interrupt Request (T4IR) MCT04825 n = 3 ... 10 Figure 6 Block Diagram of GPT1 With its maximum resolution of 8 TCL, the GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/ down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of this latch may be used to clock timer T5, and/or it may be output on pin T6OUT. The overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1, and to cause a reload from the CAPREL register. The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared Data Sheet 27 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L after the capture procedure. This allows the C161CS/JC/JI to measure absolute time differences or to perform pulse multiplication without software overhead. The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3's inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. fCPU T5IN 2n : 1 T5 Mode Control U/D GPT2 Timer T5 Clear Capture Interrupt Request (T5IR) T3 MUX CAPIN GPT2 CAPREL Interrupt Request (CRIR) CT3 Interrupt Request (T6IR) T6IN T6 Mode Control GPT2 Timer T6 U/D T6OTL T6OUT To auxiliary Timers To other Modules mcb03999b.vsd fCPU 2n : 1 n=2...9 Figure 7 Block Diagram of GPT2 Data Sheet 28 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Real Time Clock The Real Time Clock (RTC) module of the C161CS/JC/JI consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and RTCL). The RTC module is directly clocked via a separate clock driver with the on-chip main oscillator frequency divided by 32 (fRTC = fOSCm / 32) or with the on-chip auxiliary oscillator frequency (fRTC = fOSCa). It is therefore independent from the selected clock generation mode of the C161CS/JC/JI. All timers count up. The RTC module can be used for different purposes: * System clock to determine the current time and date * Cyclic time based interrupt * 48-bit timer for long term measurements T14REL Reload T14 8:1 f RTC Interrupt Request RTCH RTCL MCD04432 Figure 8 RTC Block Diagram Note: The registers associated with the RTC are not affected by a reset in order to maintain the correct system time even when intermediate resets are executed. Data Sheet 29 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L A/D Converter For analog signal measurement, a 10-bit A/D converter with 12 multiplexed input channels and a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation. The sample time (for loading the capacitors) and the conversion time is programmable and can so be adjusted to the external circuitry. Overrun error detection/protection is provided for the conversion result register (ADDAT): either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete, or the next conversion is suspended in such a case until the previous result has been read. For applications which require less than 12 analog input channels, the remaining channel inputs can be used as digital input port pins. The A/D converter of the C161CS/JC/JI supports four different conversion modes. In the standard Single Channel conversion mode, the analog level on a specified channel is sampled once and converted to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the analog levels on a prespecified number of channels (standard or extension) are sequentially sampled and converted. In the Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and converted. In addition, the conversion of a specific channel can be inserted (injected) into a running sequence without disturbing this sequence. This is called Channel Injection Mode. The Peripheral Event Controller (PEC) may be used to automatically store the conversion results into a table in memory for later evaluation, without requiring the overhead of entering and exiting interrupt routines for each data transfer. After each reset and also during normal operation the ADC automatically performs calibration cycles. This automatic self-calibration constantly adjusts the converter to changing operating conditions (e.g. temperature) and compensates process variations. These calibration cycles are part of the conversion cycle, so they do not affect the normal operation of the A/D converter. In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital IO or input stages under software control. This can be selected for each pin separately via register P5DIDIS (Port 5 Digital Input Disable). Data Sheet 30 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by three serial interfaces with different functionality, two Asynchronous/Synchronous Serial Channels (ASC0/ASC1) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with the serial ports of the Infineon 8-bit microcontroller families and supports full-duplex asynchronous communication at up to 781 kBaud and half-duplex synchronous communication at up to 3.1 MBaud (@ 25 MHz CPU clock). A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling 4 separate interrupt vectors are provided. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data plus wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. A parity bit can automatically be generated on transmission or be checked on reception. Framing error detection allows to recognize data frames with missing stop bits. An overrun error will be generated, if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete. The ASC1 is function compatible with the ASC0, except that its registers are not bitaddressable (XBUS peripheral) and it provides only three interrupt vectors. The SSC supports full-duplex synchronous communication at up to 6.25 MBaud (@ 25 MHz CPU clock). It may be configured so it interfaces with serially linked peripheral components. A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning. For transmission, reception and error handling three separate interrupt vectors are provided. The SSC transmits or receives characters of 2 ... 16 bits length synchronously to a shift clock which can be generated by the SSC (master mode) or by an external master (slave mode). The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity. A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers. Transmit and receive error supervise the correct handling of the data buffer. Phase and baudrate error detect incorrect serial data. Data Sheet 31 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Serial Data Link Module (SDLM) The Serial Data Link Module (SDLM) provides serial communication via a J1850 type multiplexed serial bus via an external J1850 bus transceiver. The module conforms to the SAE Class B J1850 specification for variable pulse width modulation (VPW). The SDLM is integrated as an on-chip peripheral and is connected to the CPU via the XBUS. General SDLM Features: * * * * * * * * * * * Compliant to the SAE Class B J1850 specification (VPW) Class 2 protocol fully supported Variable Pulse Width (VPW) operation at 10.4 kBaud High Speed 4X operation at 41.6 kBaud Programmable Normalization Bit Programmable Delay for transceiver interface Digital Noise Filter Power Down mode with automatic wakeup support upon bus activity Single Byte Header and Consolidated Header supported CRC generation and checking Receive and transmit Block Mode Data Link Operation Features: 11 Byte Transmit Buffer Double buffered 11 Byte receive buffer (optional overwrite enable) Support for In Frame Response (IFR) types 1, 2 and 3 Transmit and Receiver Message Buffers configurable for either FIFO or Byte mode Advanced Interrupt Handling with 8 separately enabled sources: Error, format or bus shorted CRC error Lost Arbitration Break received In-Frame-Response request Header received Complete message received Transmit successful * Automatic IFR transmission (Types 1 and 2) for 3-Byte consolidated headers * User configurable clock divider * Bus status flags (IDLE, EOF, EOD, SOF, Tx and Rx in progress) * * * * * Note: When the SDLM is used with the interface lines assigned to Port 4, the interface lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 ... A16. CS lines can be used to increase the total amount of addressable external memory. Data Sheet 32 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L CAN-Modules The integrated CAN-Modules handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-Modules can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The modules provide Full CAN functionality on up to 15 message objects each. Message object 15 may be configured for Basic CAN functionality. Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode. All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 bytes. The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. Each CAN-Module uses two pins of Port 4 or Port 8 to interface to an external bus transceiver. The interface pins are assigned via software. Module CAN2 (C161CS only) is identical with the first one, except that it uses a separate address area and a separate interrupt node. The two CAN modules can be internally coupled by assigning their interface pins to the same two port pins, or they can interface to separate CAN buses. Note: When one or both of the on-chip CAN Modules are used with the interface lines assigned to Port 4, the interface lines override the segment address lines and the segment address output on Port 4 is therefore limited to 6/4 bits i.e. address lines A21/A19 ... A16. CS lines can be used to increase the total amount of addressable external memory. IIC Module The integrated IIC Bus Module handles the transmission and reception of frames over the two-line IIC bus in accordance with the IIC Bus specification. The on-chip IIC Module can receive and transmit data using 7-bit or 10-bit addressing and it can operate in slave mode, in master mode or in multi-master mode. Several physical interfaces (port pins) can be established under software control. Data can be transferred at speeds up to 400 kbit/sec. Two interrupt nodes dedicated to the IIC module allow efficient interrupt service and also support operation via PEC transfers. Note: The port pins associated with the IIC interfaces feature open drain drivers only, as required by the IIC specification. Data Sheet 33 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Parallel Ports The C161CS/JC/JI provides up to 93 I/O lines which are organized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of five I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control registers, Port 9 provides open-drain-only drivers. During the internal reset, all port pins are configured as inputs. The input threshold of Port 2, Port 3, Port 4, Port 6, and Port 7 is selectable (TTL or CMOS like), where the special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input threshold may be selected individually for each byte of the respective ports. All port lines have programmable alternate input or output functions associated with them. All port lines that are not used for these alternate functions may be used as general purpose IO lines. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17 ... A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 2, Port 7, and parts of PORT1 are associated with the capture inputs or compare outputs of the CAPCOM units. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE, and the system clock output CLKOUT (or the programmable frequency output FOUT). Port 5 is used for the analog input channels to the A/D converter or timer control signals. The edge characteristics (transition time) and driver characteristics (output current) of the C161CS/JC/JI's port drivers can be selected via the Port Output Control registers (POCONx). Data Sheet 34 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip's start-up procedure is always monitored. The software has to be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to do so, the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to be reset. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 2/4/128/ 256. The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals between 20 s and 671 ms can be monitored (@ 25 MHz). The default Watchdog Timer interval after reset is 5.24 ms (@ 25 MHz). Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions on the oscillator clock. This PLL clock is independent from the XTAL1 clock. When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock / OWD interrupt node and supplies the CPU with the PLL clock signal. Under these circumstances the PLL will oscillate with its basic frequency. In direct drive mode the PLL base frequency is used directly (fCPU = 2 ... 5 MHz). In prescaler mode the PLL base frequency is divided by 2 (fCPU = 1 ... 2.5 MHz). Note: The CPU clock source is only switched back to the oscillator clock after a hardware reset. The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON. In this case (OWDDIS = `1') the PLL remains idle and provides no clock signal, while the CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also no interrupt request will be generated in case of a missing oscillator clock. Note: At the end of an external reset (EA = `0') bit OWDDIS reflects the inverted level of pin RD at that time. Thus the oscillator watchdog may also be disabled via hardware by (externally) pulling the RD line low upon a reset, similar to the standard reset configuration via PORT0. At the end of an internal reset (EA = `1') bit OWDDIS is cleared. Data Sheet 35 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Power Management The C161CS/JC/JI provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): * Power Saving Modes switch the C161CS/JC/JI into a special operating mode (control via instructions). Idle Mode stops the CPU while the peripherals can continue to operate. Sleep Mode and Power Down Mode stop all clock signals and all operation (RTC may optionally continue running). Sleep Mode can be terminated by external interrupt signals. * Clock Generation Management controls the distribution and the frequency of internal and external clock signals (control via register SYSCON2). Slow Down Mode lets the C161CS/JC/JI run at a CPU clock frequency of fOSC / 1 ... 32 (half for prescaler operation) which drastically reduces the consumed power. The PLL can be optionally disabled while operating in Slow Down Mode. External circuitry can be controlled via the programmable frequency output FOUT. * Peripheral Management permits temporary disabling of peripheral modules (control via register SYSCON3). Each peripheral can separately be disabled/enabled. A group control option disables a major part of the peripheral set by setting one single bit. The on-chip RTC supports intermittend operation of the C161CS/JC/JI by generating cyclic wakeup signals. This offers full performance to quickly react on action requests while the intermittend sleep phases greatly reduce the average power consumption of the system. Data Sheet 36 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Instruction Set Summary Table 6 lists the instructions of the C161CS/JC/JI in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the opcodes for each instruction can be found in the "C166 Family Instruction Set Manual". This document also provides a detailled description of each instruction. Table 6 Mnemonic ADD(B) ADDC(B) SUB(B) SUBC(B) MUL(U) DIV(U) DIVL(U) CPL(B) NEG(B) AND(B) OR(B) XOR(B) BCLR BSET BMOV(N) BAND, BOR, BXOR BCMP BFLDH/L CMP(B) CMPD1/2 CMPI1/2 PRIOR SHL / SHR ROL / ROR ASHR Data Sheet Instruction Set Summary Description Add word (byte) operands Add word (byte) operands with Carry Subtract word (byte) operands Subtract word (byte) operands with Carry (Un)Signed multiply direct GPR by direct GPR (16-16-bit) (Un)Signed divide register MDL by direct GPR (16-/16-bit) (Un)Signed long divide reg. MD by direct GPR (32-/16-bit) Complement direct word (byte) GPR Negate direct word (byte) GPR Bitwise AND, (word/byte operands) Bitwise OR, (word/byte operands) Bitwise XOR, (word/byte operands) Clear direct bit Set direct bit Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 Compare word data to GPR and increment GPR by 1/2 Determine number of shift cycles to normalize direct word GPR and store result in direct word GPR Shift left/right direct word GPR Rotate left/right direct word GPR Arithmetic (sign bit) shift right direct word GPR 37 Bytes 2/4 2/4 2/4 2/4 2 2 2 2 2 2/4 2/4 2/4 2 2 4 4 4 4 2/4 2/4 2/4 2 2 2 2 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 6 Instruction Set Summary (cont'd) Description Move word (byte) data Move byte operand to word operand with sign extension Move byte operand to word operand. with zero extension Jump absolute/indirect/relative if condition is met Jump absolute to a code segment Jump relative if direct bit is (not) set Jump relative and clear bit if direct bit is set Jump relative and set bit if direct bit is not set Call absolute/indirect/relative subroutine if condition is met Call absolute subroutine in any code segment Push direct word register onto system stack and call absolute subroutine Call interrupt service routine via immediate trap number Push/pop direct word register onto/from system stack Push direct word register onto system stack and update register with word operand Return from intra-segment subroutine Return from inter-segment subroutine Return from intra-segment subroutine and pop direct word register from system stack Return from interrupt service subroutine Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence Null operation Bytes 2/4 2/4 2/4 4 4 4 4 4 4 4 4 2 2 4 2 2 2 2 4 4 4 4 4 4 2 2 2/4 2/4 2 Mnemonic MOV(B) MOVBS MOVBZ JMPA, JMPI, JMPR JMPS J(N)B JBC JNBS CALLA, CALLI, CALLR CALLS PCALL TRAP PUSH, POP SCXT RET RETS RETP RETI SRST IDLE PWRDN SRVWDT DISWDT EINIT ATOMIC EXTR EXTP(R) EXTS(R) NOP Data Sheet 38 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Special Function Registers Overview Table 7 lists all SFRs which are implemented in the C161CS/JC/JI in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". Registers within on-chip X-peripherals are marked with the letter "X" in column "Physical Address". An SFR can be specified via its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its short 8-bit address (without using the Data Page Pointers). Note: Registers within device specific interface modules (CAN, SDLM) are only present in the corresponding device, of course. Table 7 Name ADCIC ADCON ADDAT ADDAT2 ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 ADEIC BUFFCON C161CS/JC/JI Registers, Ordered by Name Physical Address b FF98H b FFA0H 8-Bit Description Addr. CCH A/D Converter End of Conversion Interrupt Control Register D0H A/D Converter Control Register A/D Converter Result Register A/D Converter 2 Result Register Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 A/D Converter Overrun Error Interrupt Control Register SDLM Buffer Control Register SDLM Buffer Status Register Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 SDLM Bus Status Register CAN1 Bit Timing Register CAN1 Control / Status Register CAN1 Global Mask Short 39 Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H UUUUH XX01H UFUUH V3.0, 2001-01 FEA0H 50H F0A0H E 50H FE18H FE1AH FE1CH FE1EH b FF9AH EB24H 0CH 0DH 0EH 0FH CDH X --- BUFFSTAT EB1CH X --BUSCON0 b FF0CH 86H BUSCON1 b FF14H BUSCON2 b FF16H BUSCON3 b FF18H BUSCON4 b FF1AH BUSSTAT C1BTR C1CSR C1GMS Data Sheet 8AH 8BH 8CH 8DH X --X --X --X --- EB20H EF04H EF00H EF06H C161CS/JC/JI-32R C161CS/JC/JI-L Table 7 Name C1PCIR C1LARn C1LGML C1LMLM C1MCFGn C1MCRn C1UARn C1UGML C1UMLM C2BTR C2CSR C2GMS C2PCIR C2LARn C2LGML C2LMLM C2MCFGn C2MCRn C2UARn C2UGML C2UMLM CAPREL CC0 CC0IC CC1 CC10 CC10IC CC11 CC11IC CC12 CC12IC CC13 Data Sheet C161CS/JC/JI Registers, Ordered by Name (cont'd) Physical 8-Bit Description Address Addr. EF02H X --CAN1 Port Control / Interrupt Register EFn4H X --EF0AH X --EF0EH X --EFn6H X --EFn0H EFn2H X --X --CAN1 Lower Arbitration Reg. (msg. n) CAN1 Lower Global Mask Long CAN1 Lower Mask of Last Message CAN1 Message Config. Reg. (msg. n) CAN1 Message Control Reg. (msg. n) CAN1 Upper Arbitration Reg. (msg. n) CAN1 Upper Global Mask Long CAN1 Upper Mask of Last Message CAN2 Bit Timing Register CAN2 Control / Status Register CAN2 Global Mask Short CAN2 Port Control / Interrupt Register CAN2 Lower Arbitration Reg. (msg. n) CAN2 Lower Global Mask Long CAN2 Lower Mask of Last Message CAN2 Message Config. Reg. (msg. n) CAN2 Message Control Reg. (msg. n) CAN2 Upper Arbitration Reg. (msg. n) CAN2 Upper Global Mask Long CAN2 Upper Mask of Last Message GPT2 Capture/Reload Register CAPCOM Register 0 CAPCOM Register 0 Interrupt Ctrl. Reg. CAPCOM Register 1 CAPCOM Register 10 CAPCOM Reg. 10 Interrupt Ctrl. Reg. CAPCOM Register 11 CAPCOM Reg. 11 Interrupt Ctrl. Reg. CAPCOM Register 12 CAPCOM Reg. 12 Interrupt Ctrl. Reg. CAPCOM Register 13 40 Reset Value XXXXH UUUUH UUUUH UUUUH UUH UUUUH UUUUH UUUUH UUUUH UUUUH XX01H UFUUH XXXXH UUUUH UUUUH UUUUH UUH UUUUH UUUUH UUUUH UUUUH 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H V3.0, 2001-01 EF08H X --EF0CH X --EE04H EE00H EE06H EE02H X --X --X --X --- EEn4H X --EE0AH X --EE0EH X --EEn6H X --EEn0H EEn2H X --X --- EE08H X --EE0CH X --FE4AH FE80H b FF78H FE82H FE94H b FF8CH FE96H b FF8EH FE98H b FF90H FE9AH 25H 40H BCH 41H 4AH C6H 4BH C7H 4CH C8H 4DH C161CS/JC/JI-32R C161CS/JC/JI-L Table 7 Name CC13IC CC14 CC14IC CC15 CC15IC CC16 CC16IC CC17 CC17IC CC18 CC18IC CC19 CC19IC CC1IC CC2 CC20 CC20IC CC21 CC21IC CC22 CC22IC CC23 CC23IC CC24 CC24IC CC25 CC25IC CC26 CC26IC CC27 CC27IC CC28 Data Sheet C161CS/JC/JI Registers, Ordered by Name (cont'd) Physical Address b FF92H FE9CH b FF94H FE9EH b FF96H FE60H b F160H FE62H b F162H FE64H b F164H FE66H b F166H b FF7AH FE84H FE68H b F168H 8-Bit Description Addr. C9H CAPCOM Reg. 13 Interrupt Ctrl. Reg. 4EH CAH 4FH CBH 30H E B0H 31H E B1H 32H E B2H 33H E B3H BDH 42H 34H E B4H CAPCOM Register 14 CAPCOM Reg. 14 Interrupt Ctrl. Reg. CAPCOM Register 15 CAPCOM Reg. 15 Interrupt Ctrl. Reg. CAPCOM Register 16 CAPCOM Reg.16 Interrupt Ctrl. Reg. CAPCOM Register 17 CAPCOM Reg. 17 Interrupt Ctrl. Reg. CAPCOM Register 18 CAPCOM Reg. 18 Interrupt Ctrl. Reg. CAPCOM Register 19 CAPCOM Reg. 19 Interrupt Ctrl. Reg. CAPCOM Reg. 1 Interrupt Ctrl. Reg. CAPCOM Register 2 CAPCOM Register 20 CAPCOM Reg. 20 Interrupt Ctrl. Reg. CAPCOM Register 21 CAPCOM Reg. 21 Interrupt Ctrl. Reg. CAPCOM Register 22 CAPCOM Reg. 22 Interrupt Ctrl. Reg. CAPCOM Register 23 CAPCOM Reg. 23 Interrupt Ctrl. Reg. CAPCOM Register 24 CAPCOM Reg. 24 Interrupt Ctrl. Reg. CAPCOM Register 25 CAPCOM Reg. 25 Interrupt Ctrl. Reg. CAPCOM Register 26 CAPCOM Reg. 26 Interrupt Ctrl. Reg. CAPCOM Register 27 CAPCOM Reg. 27 Interrupt Ctrl. Reg. CAPCOM Register 28 41 Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H V3.0, 2001-01 FE6AH 35H b F16AH E B5H FE6CH 36H b F16CH E B6H FE6EH 37H b F16EH E B7H FE70H 38H b F170H E B8H FE72H b F172H FE74H b F174H FE76H b F176H FE78H 39H E B9H 3AH E BAH 3BH E BBH 3CH C161CS/JC/JI-32R C161CS/JC/JI-L Table 7 Name CC28IC CC29 CC29IC CC2IC CC3 CC30 CC30IC CC31 CC31IC CC3IC CC4 CC4IC CC5 CC5IC CC6 CC6IC CC7 CC7IC CC8 CC8IC CC9 CC9IC CCM0 CCM1 CCM2 CCM3 CCM4 CCM5 CCM6 CCM7 CLKDIV CP Data Sheet C161CS/JC/JI Registers, Ordered by Name (cont'd) Physical 8-Bit Description Address Addr. b F178H E BCH CAPCOM Reg. 28 Interrupt Ctrl. Reg. FE7AH 3DH b F184H E C2H b FF7CH FE86H BEH 43H CAPCOM Register 29 CAPCOM Reg. 29 Interrupt Ctrl. Reg. CAPCOM Reg. 2 Interrupt Ctrl. Reg. CAPCOM Register 3 CAPCOM Register 30 CAPCOM Reg. 30 Interrupt Ctrl. Reg. CAPCOM Register 31 CAPCOM Reg. 31 Interrupt Ctrl. Reg. CAPCOM Reg. 3 Interrupt Ctrl. Reg. CAPCOM Register 4 CAPCOM Reg. 4 Interrupt Ctrl. Reg. CAPCOM Register 5 CAPCOM Reg. 5 Interrupt Ctrl. Reg. CAPCOM Register 6 CAPCOM Reg. 6 Interrupt Ctrl. Reg. CAPCOM Register 7 CAPCOM Reg. 7 Interrupt Ctrl. Reg. CAPCOM Register 8 CAPCOM Reg. 8 Interrupt Ctrl. Reg. CAPCOM Register 9 CAPCOM Reg. 9 Interrupt Ctrl. Reg. CAPCOM Mode Control Register 0 CAPCOM Mode Control Register 1 CAPCOM Mode Control Register 2 CAPCOM Mode Control Register 3 CAPCOM Mode Control Register 4 CAPCOM Mode Control Register 5 CAPCOM Mode Control Register 6 CAPCOM Mode Control Register 7 SDLM Clock Divider Register CPU Context Pointer Register 42 Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H FC00H V3.0, 2001-01 FE7CH 3EH b F18CH E C6H FE7EH 3FH b F194H E CAH b FF7EH BFH FE88H 44H b FF80H FE8AH b FF82H FE8CH b FF84H FE8EH b FF86H FE90H b FF88H FE92H b FF8AH b FF52H b FF54H b FF56H b FF58H b FF22H b FF24H b FF26H b FF28H EB14H FE10H C0H 45H C1H 46H C2H 47H C3H 48H C4H 49H C5H A9H AAH ABH ACH 91H 92H 93H 94H X --08H C161CS/JC/JI-32R C161CS/JC/JI-L Table 7 Name CRIC CSP DP0H DP0L DP1H DP1L DP2 DP3 DP4 DP6 DP7 DP9 DPP0 DPP1 DPP2 DPP3 C161CS/JC/JI Registers, Ordered by Name (cont'd) Physical Address b FF6AH FE08H b F102H b F100H b F106H b F104H b FFC2H b FFC6H b FFCAH b FFCEH b FFD2H b FFDAH FE00H FE02H FE04H FE06H 8-Bit Description Addr. B5H GPT2 CAPREL Interrupt Ctrl. Reg. 04H E 81H E 80H E 83H E 82H E1H E3H E5H E7H E9H EDH 00H 01H 02H 03H CPU Code Segment Pointer Register (8 bits, not directly writeable) P0H Direction Control Register P0L Direction Control Register P1H Direction Control Register P1L Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register Port 7 Direction Control Register Port 9 Direction Control Register CPU Data Page Pointer 0 Reg. (10 bits) CPU Data Page Pointer 1 Reg. (10 bits) CPU Data Page Pointer 2 Reg. (10 bits) CPU Data Page Pointer 3 Reg. (10 bits) SDLM Error Status Register External Interrupt Control Register External Interrupt Source Select Register SDLM Flag Reset Register Frequency Output Control Register SDLM Global Control Register IIC Address Register IIC Configuration Register IIC Control Register IIC Receive/Transmit Buffer IIC Status Register Identifier Identifier Identifier Reset Value 0000H 0000H 00H 00H 00H 00H 0000H 0000H 00H 00H 00H 00H 0000H 0001H 0002H 0003H 0000H 0000H 0000H 0000H 0000H 0000H 0XXXH XX00H 0000H XXH 0000H 1XXXH 1820H X040H ERRSTAT EB22H EXICON b F1C0H EXISEL FLAGRST X --E E0H b F1DAH E EDH EB28H X --- FOCON b FFAAH D5H GLOBCON EB10H X --ICADR ICCFG ICCON ICRTB ICST IDCHIP IDMANUF IDMEM ED06H X --ED00H X --ED02H X --ED08H X --ED04H X --F07CH E 3EH F07EH F07AH E 3FH E 3DH Data Sheet 43 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 7 Name IDPROG IFR INTCON IPCR ISNC MDC MDH MDL ODP2 ODP3 ODP4 ODP6 ODP7 ONES P0H P0L P1H P1L P2 P3 P4 P5 P6 P7 P9 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 Data Sheet C161CS/JC/JI Registers, Ordered by Name (cont'd) Physical 8-Bit Description Address Addr. F078H E 3CH Identifier EB18H X --EB2CH X --EB04H X --F1DEH E EFH b FF0EH FE0CH 87H 06H SDLM In-Frame Response Register SDLM Interrupt Control Register SDLM Interface Port Connect Register Interrupt Subnode Control Register CPU Multiply Divide Control Register CPU Multiply Divide Reg. - High Word CPU Multiply Divide Reg. - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 4 Open Drain Control Register Port 6 Open Drain Control Register Port 7 Open Drain Control Register Constant Value 1's Register (read only) Port 0 High Reg. (Upper half of PORT0) Port 0 Low Reg. (Lower half of PORT0) Port 1 High Reg. (Upper half of PORT1) Port 1 Low Reg. (Lower half of PORT1) Port 2 Register Port 3 Register Port 4 Register (7 bits) Port 5 Register (read only) Port 6 Register (8 bits) Port 7 Register (8 bits) Port 9 Register (8 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register 44 Reset Value XXXXH 0000H 0000H 0007H 0000H 0000H 0000H 0000H 0000H 0000H 00H 00H 00H FFFFH 00H 00H 00H 00H 0000H 0000H 00H XXXXH 00H 00H 00H 0000H 0000H 0000H 0000H 0000H 0000H 0000H V3.0, 2001-01 FE0EH 07H b F1C2H E E1H b F1C6H E E3H b F1CAH E E5H b F1CEH E E7H b F1D2H E E9H b FF1EH b FF02H b FF00H b FF06H b FF04H b FFC0H b FFC4H b FFC8H b FFA2H b FFCCH b FFD0H b FFD8H FEC0H FEC2H FEC4H FEC6H FEC8H FECAH FECCH 8FH 81H 80H 83H 82H E0H E2H E4H D1H E6H E8H ECH 60H 61H 62H 63H 64H 65H 66H C161CS/JC/JI-32R C161CS/JC/JI-L Table 7 Name PECC7 C161CS/JC/JI Registers, Ordered by Name (cont'd) Physical Address FECEH 8-Bit Description Addr. 67H PEC Channel 7 Control Register Port Input Threshold Control Register P0L Output Control Register P0H Output Control Register P1L Output Control Register P1H Output Control Register Port 2 Output Control Register Dedicated Pins Output Control Register Port 3 Output Control Register Port 4 Output Control Register Port 6 Output Control Register Port 7 Output Control Register CPU Program Status Word System Startup Configuration Register (Rd. only) Reset Control Register RTC High Register RTC Low Register SDLM Bus Receive Byte Counter (CPU) SDLM Bus Receive Byte Counter (bus) SDLM CPU Receive Byte Counter Reg. SDLM Receive Data Register 00 (CPU) SDLM Receive Data Register 010 (CPU) SDLM Receive Data Register 02 (CPU) SDLM Receive Data Register 04 (CPU) SDLM Receive Data Register 06 (CPU) SDLM Receive Data Register 08 (CPU) SDLM Receive Data Register 10 (bus) SDLM Receive Data Register 110 (bus) SDLM Receive Data Register 12 (bus) SDLM Receive Data Register 14 (bus) SDLM Receive Data Register 16 (bus) Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H XXH 00XXH no no 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H PICON b F1C4H POCON0H F082H POCON0L POCON1H POCON1L POCON2 POCON20 POCON3 POCON4 POCON6 POCON7 PSW RP0H RSTCON RTCH RTCL RXCNT RXCNTB RXCPU RXD00 RXD010 RXD02 RXD04 RXD06 RXD08 RXD10 RXD110 RXD12 RXD14 RXD16 F080H F086H F084H F088H E E2H E 41H E 40H E 43H E 42H E 44H F0AAH E 55H F08AH E 45H F08CH F08EH F090H b FF10H b F108H E 46H E 47H E 48H 88H E 84H b F1E0H m --F0D6H E 6BH F0D4H E 6AH EB4CH X --EB4AH X --EB4EH X --EB40H X --EB4AH X --EB42H EB44H EB46H EB48H X --X --X --X --- EB50H X --EB5AH X --EB52H EB54H EB56H X --X --X --- Data Sheet 45 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 7 Name RXD18 S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC S1BG S1CON S1RBUF S1TBUF SOFPTR SP SSCBR SSCCON SSCEIC SSCRB SSCRIC SSCTB SSCTIC STKOV STKUN Data Sheet C161CS/JC/JI Registers, Ordered by Name (cont'd) Physical 8-Bit Description Address Addr. EB58H X --SDLM Receive Data Register 18 (bus) FEB4H b FFB0H b FF70H FEB2H b FF6EH b F19CH FEB0H b FF6CH 5AH D8H B8H 59H B7H E CEH 58H B6H Serial Channel 0 Baud Rate Generator Reload Register Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Ctrl. Reg. Serial Channel 0 Receive Buffer Register (read only) Serial Channel 0 Receive Interrupt Control Register Serial Channel 0 Transmit Buffer Interrupt Control Register Serial Channel 0 Transmit Buffer Register Serial Channel 0 Transmit Interrupt Control Register Serial Channel 1 Baud Rate Generator Reload Register Serial Channel 1 Control Register Serial Channel 1 Receive Buffer Register (read only) Serial Channel 1 Transmit Buffer Register SDLM Start-of-Frame Pointer Register CPU System Stack Pointer Register SSC Baudrate Register SSC Control Register SSC Error Interrupt Control Register SSC Receive Buffer (read only) SSC Receive Interrupt Control Register SSC Transmit Buffer (write only) SSC Transmit Interrupt Control Register CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register 46 Reset Value 0000H 0000H 0000H 0000H XXXXH 0000H 0000H 0000H 0000H 0000H 0000H XXXXH 0000H 0000H FC00H 0000H 0000H 0000H XXXXH 0000H 0000H 0000H FA00H FC00H EDA4H X --EDA6H X --EDA2H X --EDA0H X --EB60H FE12H F0B4H b FFB2H b FF76H F0B2H b FF74H F0B0H b FF72H FE14H FE16H X --09H E 5AH D9H BBH E 59H BAH E 58H B9H 0AH 0BH V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Table 7 Name SYSCON C161CS/JC/JI Registers, Ordered by Name (cont'd) Physical Address b FF12H 8-Bit Description Addr. 89H CPU System Configuration Register CPU System Configuration Register 1 CPU System Configuration Register 2 CPU System Configuration Register 3 CAPCOM Timer 0 Register CAPCOM Timer 0 and Timer 1 Ctrl. Reg. CAPCOM Timer 0 Interrupt Ctrl. Reg. CAPCOM Timer 0 Reload Register CAPCOM Timer 1 Register RTC Timer 14 Register RTC Timer 14 Reload Register CAPCOM Timer 1 Interrupt Ctrl. Reg. CAPCOM Timer 1 Reload Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register CAPCOM Timer 7 Register CAPCOM Timer 7 and 8 Ctrl. Reg. CAPCOM Timer 7 Interrupt Ctrl. Reg. CAPCOM Timer 7 Reload Register 47 Reset Value 1) 0XX0H 0000H 0000H 0X00H 0000H 0000H 0000H 0000H 0000H no no 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H V3.0, 2001-01 SYSCON1 b F1DCH E EEH SYSCON2 b F1D0H E E8H SYSCON3 b F1D4H T0 FE50H T01CON T0IC T0REL T1 T14 T14REL T1IC T1REL T2 T2CON T2IC T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC T7 T78CON T7IC T7REL Data Sheet E EAH 28H A8H CEH 2AH 29H E 69H E 68H CFH 2BH 20H A0H B0H 21H A1H B1H 22H A2H B2H 23H A3H B3H 24H A4H B4H E 28H 90H E BDH E 2AH b FF50H b FF9CH FE54H FE52H F0D2H F0D0H b FF9EH FE56H FE40H b FF40H b FF60H FE42H b FF42H b FF62H FE44H b FF44H b FF64H FE46H b FF46H b FF66H FE48H b FF48H b FF68H F050H b FF20H b F17AH F054H C161CS/JC/JI-32R C161CS/JC/JI-L Table 7 Name T8 T8IC T8REL C161CS/JC/JI Registers, Ordered by Name (cont'd) Physical 8-Bit Description Address Addr. F052H E 29H CAPCOM Timer 8 Register b F17CH F056H E BEH E 2BH CAPCOM Timer 8 Interrupt Ctrl. Reg. CAPCOM Timer 8 Reload Register Trap Flag Register SDLM Transmission Status Register SDLM Bus Transmit Byte Counter Reg. SDLM CPU Transmit Byte Counter Reg. SDLM Transmit Data Register 0 SDLM Transmit Data Register 10 SDLM Transmit Data Register 2 SDLM Transmit Data Register 4 SDLM Transmit Data Register 6 SDLM Transmit Data Register 8 SDLM Transceiver Delay Register Watchdog Timer Register (read only) Watchdog Timer Control Register IIC Data Interrupt Control Register IIC Protocol Interrupt Control Register CAN1 Interrupt Control Register PLL/RTC Interrupt Control Register ASC1 Transmit Interrupt Ctrl. Reg. ASC1 Receive Interrupt Control Register ASC1 Error Interrupt Control Register CAN2/SDLM Interrupt Control Register Constant Value 0's Register (read only) Reset Value 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0014H 0000H 2)00XX H TFR b FFACH D6H TRANSSTAT EB1EH X --TXCNT TXCPU TXD0 TXD10 TXD2 TXD4 TXD6 TXD8 TxDELAY WDT WDTCON XP0IC XP1IC XP2IC XP3IC XP4IC XP5IC XP6IC XP7IC ZEROS 1) 2) EB3CH X --EB3EH X --EB30H X --EB3AH X --EB32H EB34H EB36H EB38H X --X --X --X --- EB16H X --FEAEH 57H b FFAEH D7H b F186H E C3H b F18EH b F196H b F19EH b F182H b F18AH b F192H E C7H E CBH E CFH E C1H E C5H E C9H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H b F19AH E CDH b FF1CH 8EH The system configuration is selected during reset. The reset value depends on the indicated reset source. Data Sheet 48 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Absolute Maximum Ratings Table 8 Parameter Storage temperature Junction temperature Voltage on VDD pins with respect to ground (VSS) Voltage on any pin with respect to ground (VSS) Input current on any pin during overload condition Absolute sum of all input currents during overload condition Power dissipation Absolute Maximum Rating Parameters Symbol Limit Values min. max. 150 150 6.5 C C V - under bias - - - - -65 -40 -0.5 -0.5 -10 - Unit Notes TST TJ VDD VIN - - VDD + 0.5 V 10 |100| mA mA PDISS - 1.5 W - Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < VSS) the voltage on VDD pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Data Sheet 49 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the C161CS/JC/JI. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Table 9 Parameter Digital supply voltage Operating Condition Parameters Symbol Limit Values min. max. 5.5 5.5 0 - - - 0 -40 -40 1) 2) Unit Notes V V V mA mA pF C C C Active mode, fCPUmax = 25 MHz PowerDown mode Reference voltage Per pin2)3)4) 3) VDD 4.5 2.51) Digital ground voltage Overload current Absolute sum of overload currents External Load Capacitance Ambient temperature VSS IOV |IOV| 5 50 100 70 85 125 CL TA Pin drivers in fast edge mode5) SAB-C161CS/JC/JI ... SAF-C161CS/JC/JI ... SAK-C161CS/JC/JI ... Output voltages and output currents will be reduced when VDD leaves the range defined for active mode. Overload conditions occur if the standard operatings conditions are exceeded, i.e. the voltage on any pin exceeds the specified range (i.e. VOV > VDD + 0.5 V or VOV < VSS - 0.5 V). The absolute sum of input overload currents on all pins may not exceed 50 mA. The supply voltage must remain within the specified limits. Proper operation is not guaranteed if overload conditions occur on functional pins line XTAL1, RD, WR, etc. Not 100% tested, guaranteed by design and characterization. Due to the different port structure of Port 9 (required by the IIC bus specification) the pins of Port 9 can only tolerate positive overload current, i.e. VOV > VSS - 0.5 V. The timing is valid for pin drivers in high current or dynamic current mode. The reduced static output current in dynamic current mode must be respected when designing the system. 3) 4) 5) Data Sheet 50 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161CS/ JC/JI and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the C161CS/JC/JI will provide signals with the respective timing characteristics. SR (System Requirement): The external system must provide signals with the respective timing characteristics to the C161CS/JC/JI. DC Characteristics (Operating Conditions apply)1) Parameter Symbol Limit Values min. max. 0.2 VDD V - 0.1 0.3 VDD V 2.0 V V - - - - Unit Test Condition VIL Input low voltage (TTL, all except XTAL1, XTAL3, Port 9) Input low voltage XTAL1, XTAL3, Port 9 Input low voltage (Special Threshold) Input high voltage (TTL, all except RSTIN, XTAL1, XTAL3, Port 9) Input high voltage RSTIN (when operated as input) Input high voltage XTAL1, XTAL3, Port 9 Input high voltage (Special Threshold) Input Hysteresis (Special Threshold) Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT, RSTIN2)) Output low voltage (Port 9) Data Sheet SR -0.5 VIL2 SR -0.5 VILS SR -0.5 VIH SR 0.2 VDD VDD + + 0.9 0.5 VIH1 SR 0.6 VDD VDD + 0.5 V V V mV V - - - Series resistance =0 VIH2 SR 0.7 VDD VDD + 0.5 VIHS SR 0.8 VDD VDD + - 0.2 HYS 400 0.5 - 0.45 VOL CC - IOL = 2.4 mA3) IOL = 0.5 mA4) VOL9 CC - 0.4 V IOL = 3.0 mA 51 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L DC Characteristics (cont'd) (Operating Conditions apply)1) Parameter Output low voltage (all other outputs) Output high voltage5) (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output high voltage5) (all other outputs) Input leakage current (Port 5) Input leakage current (all other) RSTIN inactive current6) RSTIN active current6) READY/RD/WR inact. current9) READY/RD/WR active current9) ALE inactive current9) ALE active current9) Port 6 inactive current9) Port 6 active current9) PORT0 configuration XTAL1 input current Pin capacitance11) (digital inputs/outputs) 1) Symbol Limit Values min. max. 0.45 - Unit Test Condition V V V V V nA nA A A A A A A A A A A A pF VOL1 CC - VOH CC 2.4 0.9 VDD - IOL = 1.6 mA3) IOL = 1.6 mA4) IOH = -2.4 mA3) IOH = -0.5 mA4) IOH = -0.5 mA3) IOH = -1.6 mA3) IOH = -0.5 mA4) IOH = -0.5 mA3) 0 V < VIN < VDD 0.45 V < VIN < VDD VIN = VIH1 VIN = VIL VOUT = 2.4 V VOUT = VOLmax VOUT = VOLmax VOUT = 2.4 V VOUT = 2.4 V VOUT = VOL1max VIN = VIHmin VIN = VILmax 0 V < VIN < VDD f = 1 MHz TA = 25 C VOH1 CC 2.4 - 0.9 VDD - IOZ1 CC - IOZ2 CC - IRSTH7) IRSTL8) IRWH 7) IRWL8) IALEL7) IALEH8) IP6H7) IP6L8) IP0H7) IP0L8) IIL CC CIO CC - -100 - -500 - 500 - -500 - -100 - - 200 500 -10 - -40 - 40 - -40 - -10 - 20 10 current10) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal levels outside these specifications also refer to the specification of the overload current IOV. Valid in bidirectional reset mode only. This output current may be drawn from (output) pins operating in High Current mode. This output current may be drawn from (output) pins operating in Low Current mode. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) 3) 4) 5) Data Sheet 52 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L 6) 7) 8) 9) These parameters describe the RSTIN pullup, which equals a resistance of ca. 50 to 250 k. The maximum current may be drawn while the respective signal line remains inactive. The minimum current must be drawn in order to drive the respective signal line active. This specification is valid during Reset and during Hold-mode or Adapt-mode. During Hold-mode Port 6 pins are only affected, if they are used (configured) for CS output and the open drain function is not enabled. The READY-pullup is always active, except for Powerdown mode. This specification is valid during Reset and during Adapt-mode. Not 100% tested, guaranteed by design and characterization. 10) 11) Power Consumption C161CS/JC/JI (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Symbol Limit Values min. max. 15 + mA 2.5 x fCPU 5+ mA 1.5 x fCPU 500 + 50 x fOSC 100 A RSTIN = VIL fCPU in [MHz]1) RSTIN = VIH1 fCPU in [MHz]1) RSTIN = VIH1 fOSC in [MHz]1) - - - Unit Test Condition IDD IIDX Idle mode supply curr., Main osc, IIDOM2) with all peripherals deactivated, PLL off, SDD factor = 32 Idle mode supply curr., Aux. osc, IIDOA2) with all peripherals deactivated, PLL off, SDD factor = 32 Sleep and Power-down mode IPDRM2) supply current with RTC running on main oscillator Sleep and Power-down mode IPDO supply current with RTC disabled 1) - A VDD = VDDmax fOSC = 32 kHz3) VDD = VDDmax fOSC in [MHz]3) VDD = VDDmax3) - 200 + 25 x fOSC 50 A - A The supply current is a function of the operating frequency. This dependency is illustrated in Figure 10. These parameters are tested at VDDmax and maximum CPU clock with all outputs disconnected and all inputs at VIL or VIH. This parameter is determined mainly by the current consumed by the oscillator (see Figure 9). This current, however, is influenced by the external oscillator circuitry (crystal, capacitors). The values given refer to a typical circuitry and may change in case of a not optimized external oscillator circuitry. This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, all outputs (including pins configured as outputs) disconnected. 2) 3) Data Sheet 53 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L I A 1500 1250 1000 750 500 IIDOMmax IIDOMtyp IPDRMmax 250 IIDOAmax 0 0 4 8 IPDOmax 12 16 MHz fOSC MCD04453 Figure 9 Idle and Power Down Supply Current as a Function of Oscillator Frequency Data Sheet 54 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L I [mA] 100 IDD5max 80 IDD5typ 60 IIDX5max 40 IIDX5typ 20 10 Figure 10 15 20 25 fCPU [MHz] Supply/Idle Current as a Function of Operating Frequency Data Sheet 55 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L AC Characteristics Definition of Internal Timing The internal operation of the C161CS/JC/JI is controlled by the internal CPU clock fCPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external timing (AC Characteristics) therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see Figure 11). Phase Locked Loop Operation fOSC TCL fCPU TCL Direct Clock Drive fOSC TCL fCPU TCL Prescaler Operation fOSC TCL fCPU TCL MCT04338 Figure 11 Generation Mechanisms for the CPU Clock The CPU clock signal fCPU can be generated from the oscillator clock signal fOSC via different mechanisms. The duration of TCLs and their variation (and also the derived external timing) depends on the used mechanism to generate fCPU. This influence must be regarded when calculating the timings for the C161CS/JC/JI. Note: The example for PLL operation shown in the fig. above refers to a PLL factor of 4. The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG in register RP0H.7-5. Upon a long hardware reset register RP0H is loaded with the logic levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins Data Sheet 56 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L P0.15-13 (P0H.7-5). Register RP0H can be loaded from the upper half of register RSTCON under software control. Table 10 associates the combinations of these three bits with the respective clock generation mode. Table 10 CLKCFG (P0H.7-5) 111 110 101 100 011 010 001 000 1) 2) C161CS/JC/JI Clock Generation Modes CPU Frequency External Clock fCPU = fOSC x F Input Range1) Notes Default configuration - - - Direct drive2) - CPU clock via prescaler - fOSC x 4 fOSC x 3 fOSC x 2 fOSC x 5 fOSC x 1 fOSC x 1.5 fOSC / 2 fOSC x 2.5 2.5 to 6.25 MHz 3.33 to 8.33 MHz 5 to 12.5 MHz 2 to 5 MHz 1 to 25 MHz 6.66 to 16.6 MHz 2 to 50 MHz 4 to 10 MHz The external clock input range refers to a CPU clock range of 10 ... 25 MHz. The maximum frequency depends on the duty cycle of the external clock signal. Prescaler Operation When prescaler operation is configured (CLKCFG = 001B) the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fOSC and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fOSC. The timings listed in the AC Characteristics that refer to TCLs therefore can be calculated using the period of fOSC for any TCL. Phase Locked Loop When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fOSC x F). With every F'th transition of fOSC the PLL circuit synchronizes the CPU clock to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency does not change abruptly. Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked to fOSC. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs. Data Sheet 57 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator) the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula and Figure 12). For a period of N x TCL the minimum value is computed using the corresponding deviation DN: (N x TCL)min = N x TCLNOM - DN where N = number of consecutive TCLs DN [ns] = (13.3 + N x 6.3) / fCPU [MHz], and 1 N 40. So for a period of 3 TCLs @ 25 MHz (i.e. N = 3): D3 = (13.3 + 3 x 6.3) / 25 = 1.288 ns, and (3TCL)min = 3TCLNOM - 1.288 ns = 58.7 ns (@ fCPU = 25 MHz). This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible. Note: For all periods longer than 40 TCL the N = 40 value can be used (see Figure 12). Max. jitter DN ns 30 26.5 This approximated formula is valid for 1 < N < 40 and 10 MHz < fCPU < 25 MHz. -- - - 10 MHz 20 16 MHz 20 MHz 25 MHz 10 1 1 10 20 30 40 N MCD04455 Figure 12 Data Sheet Approximated Maximum Accumulated PLL Jitter 58 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Direct Drive When direct drive is configured (CLKCFG = 011B) the on-chip phase locked loop is disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fOSC so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fOSC. The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. This minimum value can be calculated via the following formula: (DC = duty cycle) TCLmin = 1/fOSC x DCmin For two consecutive TCLs the deviation caused by the duty cycle of fOSC is compensated so the duration of 2TCL is always 1/fOSC. The minimum value TCLmin therefore has to be used only once for timings that require an odd number of TCLs (1, 3, ...). Timings that require an even number of TCLs (2, 4, ...) may use the formula 2TCL = 1/fOSC. Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of TCL (TCLmax = 1/fOSC x DCmax) instead of TCLmin. Data Sheet 59 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L AC Characteristics External Clock Drive XTAL1 (Main Oscillator) (Operating Conditions apply) Table 11 Parameter External Clock Drive Characteristics Symbol Direct Drive 1:1 min. Oscillator period tOSCM SR 40 High time 2) Prescaler 2:1 min. 20 6 6 - - max. - - - 6 6 min. 60 10 10 - - 1) PLL 1:N max. 5001) - - 10 10 Unit max. - - - 10 10 ns ns ns ns ns Low time2) Rise time2) Fall time2) 1) t1 t2 t3 t4 SR 20 SR - SR - 3) SR 203) The minimum and maximum oscillator periods for PLL operation depend on the selected CPU clock generation mode. Please see respective table above. The clock input signal must reach the defined levels VIL2 and VIH2. The minimum high and low time refers to a duty cycle of 50%. The maximum operating frequency (fCPU) in direct drive mode depends on the duty cycle of the clock input signal. 2) 3) t1 0.5 VDD t3 t4 VIH2 VIL t2 t OSC MCT02534 Figure 13 External Clock Drive XTAL1 Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 16 MHz. It is strongly recommended to measure the oscillation allowance (or margin) in the final target system (layout) to determine the optimum parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested). Data Sheet 60 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L AC Characteristics External Clock Drive XTAL3 (Auxiliary Oscillator) (Operating Conditions apply) Table 12 Parameter AC Characteristics Symbol Optimum Input Clock Variable Input Clock = 32 kHz 1 / tOSCA = 10 to 50 kHz min. Oscillator period tOSCA SR 31 High time Low time Rise time Fall time 1) Unit max. 31 - - 12 12 min. 20 0.2 x tOSCA1) 0.2 x tOSCA1) - - max. 100 - - s s s t1 t2 t3 t4 SR 6 SR - SR - 1) SR 61) 0.4 x tOSCA s 0.4 x tOSCA s The clock input signal must reach the defined levels VIL and VIH2. Note: The auxiliary oscillator is optimized for oscillation with a crystal at a frequency of 32 kHz. When driven by an external clock signal it will accept the specified frequency range. Operation at lower input frequencies is possible but is guaranteed by design only (not 100% tested). Data Sheet 61 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L A/D Converter Characteristics (Operating Conditions apply) Table 13 Parameter Analog reference supply Analog reference ground Analog input voltage range Basic clock frequency Conversion time Calibration time after reset Total unadjusted error Internal resistance of reference voltage source A/D Converter Characteristics Symbol Limit Values min. max. 4.0 Unit Test Condition 1) VAREF SR VAGND SR VAIN SR fBC tC CC tCAL VSS - 0.1 VAGND 0.5 - VDD + 0.1 V VSS + 0.2 V VAREF V 6.25 40 tBC + - tS + 2tCPU 3328 tBC 2 - k k pF 2) MHz 3) 4) tCPU = 1 / fCPU 5) CC - TUE CC - LSB 1) RAREF SR - tBC / 60 - 0.25 tBC in [ns]6)7) tS in [ns]7)8) 7) Internal resistance of analog RASRC SR - source ADC input capacitance 1) tS / 450 - 0.25 33 CAIN CC - TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VDD = 4.9 V. It is guaranteed by design for all other voltages within the defined voltage range. If the analog reference supply voltage exceeds the power supply voltage by up to 0.2 V (i.e. VAREF = VDD = +0.2 V) the maximum TUE is increased to 3 LSB. This range is not 100% tested. The specified TUE is guaranteed only if the absolute sum of input overload currents on Port 5 pins (see IOV specification) does not exceed 10 mA. During the reset calibration sequence the maximum TUE may be 4 LSB. 2) VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these cases will be X000H or X3FFH, respectively. The limit values for fBC must not be exceeded when selecting the CPU frequency and the ADCTC setting. This parameter includes the sample time tS, the time for determining the digital result and the time to load the result register with the conversion result. Values for the basic clock tBC depend on programming and can be taken from Table 14. This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum. During the reset calibration conversions can be executed (with the current accuracy). The time required for these conversions is added to the total reset calibration time. During the conversion the ADC's capacitance must be repeatedly charged or discharged. The internal resistance of the reference voltage source must allow the capacitance to reach its respective voltage level within each conversion step. The maximum internal resistance results from the programmed conversion timing. Not 100% tested, guaranteed by design and characterization. 3) 4) 5) 6) 7) Data Sheet 62 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L 8) During the sample time the input capacitance CAIN can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result. Values for the sample time tS depend on programming and can be taken from Table 14. Sample time and conversion time of the C161CS/JC/JI's A/D Converter are programmable. Table 14 should be used to calculate the above timings. The limit values for fBC must not be exceeded when selecting ADCTC. Table 14 A/D Converter Computation Table A/D Converter Basic Clock fBC ADCON.13|12 Sample time tS (ADSTC) 00 01 10 11 ADCON.15|14 (ADCTC) 00 01 10 11 fCPU / 4 fCPU / 2 fCPU / 16 fCPU / 8 tBC x 8 tBC x 16 tBC x 32 tBC x 64 Converter Timing Example: Assumptions: Basic clock Sample time Conversion time fCPU fBC tS tC = 25 MHz (i.e. tCPU = 40 ns), ADCTC = `00', ADSTC = `00'. = fCPU / 4 = 6.25 MHz, i.e. tBC = 160 ns. = tBC x 8 = 1280 ns. = tS + 40 tBC + 2 tCPU = (1280 + 6400 + 80) ns = 7.8 s. Data Sheet 63 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Testing Waveforms 2.4 V 1.8 V Test Points 1.8 V 0.45 V 0.8 V 0.8 V AC inputs during testing are driven at 2.4 V for a logic 1' and 0.45 V for a logic 0'. Timing measurements are made at VIH min for a logic 1' and VIL max for a logic 0'. ' MCA04414 Figure 14 Input Output Waveforms VLoad + 0.1 V Timing Reference Points VOH - 0.1 V VLoad - 0.1 V VOL + 0.1 V For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs, but begins to float when a 100 mV change from the loaded VOH / VOL level occurs (I OH / I OL = 20 mA). MCA00763 Figure 15 Float Waveforms Data Sheet 64 ' ' ' V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 15 Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Memory Cycle Variables Symbol Values TCL x tA tC tF Note: Please respect the maximum operating frequency of the respective derivative. AC Characteristics Multiplexed Bus (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, WR (with RW-delay) Address float after RD, WR (no RW-delay) RD, WR low time (with RW-delay) max. - - - - min. TCL - 10 + tA TCL - 16 + tA TCL - 10 + tA TCL - 10 + tA -10 + tA - - 2TCL - 10 + tC max. - - - - - 6 TCL + 6 - ns ns ns ns ns ns ns ns t5 t6 t7 t8 t9 CC 10 + tA CC 4 + tA CC 10 + tA CC 10 + tA CC -10 + tA - 6 26 - t10 CC - t11 CC - t12 CC 30 + tC Data Sheet 65 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Multiplexed Bus (cont'd) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD Data valid to WR Data hold after WR max. - 20 + tC 40 + tC 40 + tA + tC min. 3TCL - 10 + tC - - - max. - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + tF - - - - 10 - tA 3TCL - 20 + tC + 2tA - - ns ns ns ns ns ns ns ns ns ns ns ns ns t13 CC 50 + tC t14 SR - t15 SR - t16 SR - t17 SR - t18 SR 0 t19 SR - t22 CC 20 + tC t23 CC 26 + tF 50 + 2tA - + tC - 26 + tF - - - - 10 - tA 40 + tC + 2tA - - 0 - 2TCL - 20 + tC 2TCL - 14 + tF 2TCL - 14 + tF 2TCL - 14 + tF -4 - tA - ALE rising edge after RD, t25 CC 26 + tF WR Address hold after RD, WR ALE falling edge to CS1) CS low to Valid Data In1) t27 CC 26 + tF t38 CC -4 - tA t39 SR - CS hold after RD, WR1) ALE fall. edge to RdCS, WrCS (with RW delay) t40 CC 46 + tF t42 CC 16 + tA 3TCL - 14 + tF TCL - 4 + tA ns ns Data Sheet 66 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Multiplexed Bus (cont'd) (Operating Conditions apply) ALE cycle time = 6 TCL + 2tA + tC + tF (120 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. ALE fall. edge to RdCS, WrCS (no RW delay) max. - 0 20 16 + tC 36 + tC - - - - 20 + tF - - min. -4 + tA - - - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - 2TCL - 20 + tF 2TCL - 20 + tF max. - 0 TCL 2TCL - 24 + tC 3TCL - 24 + tC - - - - 2TCL - 20 + tF - - ns ns ns ns ns ns ns ns ns ns ns ns t43 CC -4 + tA Address float after RdCS, t44 CC - WrCS (with RW delay) Address float after RdCS, t45 CC - WrCS (no RW delay) RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS 1) t46 SR - t47 SR - t48 CC 30 + tC t49 CC 50 + tC t50 CC 26 + tC t51 SR 0 t52 SR - t54 CC 20 + tF t56 CC 20 + tF These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below). Data Sheet 67 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L t5 ALE t16 t25 t38 CSxL t39 t40 t17 A23-A16 (A15-A8) BHE, CSxE Address t27 t6 t7 Read Cycle BUS Address t54 t19 t18 Data IN t8 RD t10 t14 t12 t42 RdCSx t44 t46 t48 t51 t52 Write Cycle BUS Address t23 Data OUT t8 WR, WRL, WRH t10 t22 t12 t56 t42 WrCSx t44 t50 t48 MCT04439 Figure 16 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet 68 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L t5 ALE t16 t38 t39 t25 t40 CSxL t17 A23-A16 (A15-A8) BHE, CSxE Address t27 t6 t7 t18 Address Data IN t54 t19 Read Cycle BUS t8 RD t10 t14 t12 t42 RdCSx t44 t46 t48 t51 t52 Write Cycle BUS Address t23 Data OUT t8 WR, WRL, WRH t10 t22 t12 t56 t42 WrCSx t44 t50 t48 MCT04440 Figure 17 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE 69 V3.0, 2001-01 Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L t5 ALE t16 t25 t38 CSxL t39 t40 t17 A23-A16 (A15-A8) BHE, CSxE Address t27 t6 t7 Read Cycle BUS Address t54 t19 t18 Data IN t9 RD t11 t15 t13 t43 RdCSx t45 t47 t49 t51 t52 Write Cycle BUS Address t23 Data OUT t9 WR, WRL, WRH t11 t13 t22 t56 t43 WrCSx t45 t49 t50 MCT04441 Figure 18 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE 70 V3.0, 2001-01 Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L t5 ALE t16 t38 t39 t25 t40 CSxL t17 A23-A16 (A15-A8) BHE, CSxE Address t27 t6 t7 t18 Address Data IN t54 t19 Read Cycle BUS t9 t11 t15 t13 RD t43 t45 t47 t49 t51 t52 RdCSx Write Cycle BUS Address t23 Data OUT t9 WR, WRL, WRH t11 t13 t22 t56 t43 WrCSx t45 t49 t50 MCT04442 Figure 19 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE 71 V3.0, 2001-01 Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L AC Characteristics Demultiplexed Bus (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising edge (with RW-delay1)) Data float after RD rising edge (no RW-delay1)) max. - - - min. TCL - 10 + tA TCL - 16 + tA TCL - 10 + tA -10 + tA 2TCL - 10 + tC 3TCL - 10 + tC - - - max. - - - - - - 2TCL - 20 + tC 3TCL - 20 + tC 3TCL - 20 + tA + tC 4TCL - 30 + 2tA + tC - 2TCL - 14 + 22tA + tF1) TCL - 10 + 22tA + tF1) ns ns ns ns ns ns ns ns ns ns ns ns t5 t6 t8 t9 CC 10 + tA CC 4 + tA CC 10 + tA CC -10 + tA - - - 20 + tC 40 + tC 40 + t12 CC 30 + tC t13 CC 50 + tC t14 SR - t15 SR - t16 SR - t17 SR - t18 SR 0 t20 SR - tA + t C 50 + - 2tA + tC - 0 26 + - 1) 2tA + tF 10 + - 1) 2tA + tF t21 SR - ns Data Sheet 72 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Demultiplexed Bus (cont'd) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. Data valid to WR Data hold after WR max. - - - - 10 - tA min. 2TCL - 20 + tC TCL - 10 + tF -10 + tF 0 + tF -4 - tA max. - - - - 10 - tA 3TCL - 20 + tC + 2tA - - - 2TCL - 24 + tC 3TCL - 24 + tC - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t22 CC 20 + tC t24 CC 10 + tF ALE rising edge after RD, t26 CC -10 + tF WR Address hold after WR2) ALE falling edge to CS3) CS low to Valid Data In3) CS hold after RD, WR3) t28 CC 0 + tF t38 CC -4 - tA t39 SR - t41 CC 6 + tF 40 + - tC + 2tA - - - 16 + tC 36 + tC - - - - 20 + tF TCL - 14 + tF TCL - 4 + tA -4 + tA - - 2TCL - 10 + tC 3TCL - 10 + tC 2TCL - 14 + tC 0 - ALE falling edge to RdCS, t42 CC 16 + tA WrCS (with RW-delay) ALE falling edge to RdCS, t43 CC -4 + tA WrCS (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS Data hold after RdCS Data float after RdCS (with RW-delay)1) t46 SR - t47 SR - t48 CC 30 + tC t49 CC 50 + tC t50 CC 26 + tC t51 SR 0 t53 SR - 2TCL - 20 ns + 2tA + tF1) Data Sheet 73 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Demultiplexed Bus (cont'd) (Operating Conditions apply) ALE cycle time = 4 TCL + 2tA + tC + tF (80 ns at 25 MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. Data float after RdCS (no RW-delay)1) Address hold after RdCS, WrCS Data hold after WrCS 1) 2) max. 0 + tF - - min. - -6 + tF max. TCL - 20 ns 1) + 2tA + tF - ns ns t68 SR - t55 CC -6 + tF t57 CC 6 + tF TCL - 14 + - tF RW-delay and tA refer to the next following bus cycle (including an access to an on-chip X-Peripheral). Read data are latched with the same clock edge that triggers the address change and the rising RD edge. Therefore address changes before the end of RD have no impact on read cycles. These parameters refer to the latched chip select signals (CSxL). The early chip select signals (CSxE) are specified together with the address and signal BHE (see figures below). 3) Data Sheet 74 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L t5 ALE t16 t26 t38 CSxL t39 t41 t17 A23-A16 A15-A0 BHE, CSxE Address t28 t6 Read Cycle BUS (D15-D8) D7-D0 t55 t20 t18 Data IN t8 t14 t12 RD t42 RdCSx Write Cycle BUS (D15-D8) D7-D0 t46 t48 t51 t53 t24 Data OUT t8 t12 t22 t57 WR, WRL, WRH t42 t48 WrCSx t50 MCT04443 Figure 20 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE 75 V3.0, 2001-01 Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L t5 ALE t16 t38 t39 t26 t41 CSxL t17 A23-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0 Address t28 t6 t55 t20 t18 Data IN t8 t14 t12 RD t42 RdCSx Write Cycle BUS (D15-D8) D7-D0 t46 t48 t51 t53 t24 Data OUT t8 t12 t22 t57 WR, WRL, WRH t42 t48 WrCSx t50 MCT04444 Figure 21 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE 76 V3.0, 2001-01 Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L t5 ALE t16 t26 t38 CSxL t39 t41 t17 A23-A16 A15-A0 BHE, CSxE Address t28 t6 Read Cycle BUS (D15-D8) D7-D0 t55 t21 t18 Data IN t9 t15 t13 RD t43 RdCSx Write Cycle BUS (D15-D8) D7-D0 t47 t49 t51 t68 t24 Data OUT t22 t9 t13 t57 WR, WRL, WRH t43 t49 WrCSx t50 MCT04445 Figure 22 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE 77 V3.0, 2001-01 Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L t5 ALE t16 t38 t39 t26 t41 CSxL t17 A23-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0 Address t28 t6 t55 t21 t18 Data IN t9 t15 t13 RD t43 RdCSx Write Cycle BUS (D15-D8) D7-D0 t47 t49 t51 t68 t24 Data OUT t9 t13 t22 t57 WR, WRL, WRH t43 t49 WrCSx t50 MCT04446 Figure 23 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE 78 V3.0, 2001-01 Data Sheet C161CS/JC/JI-32R C161CS/JC/JI-L AC Characteristics CLKOUT and READY (Operating Conditions apply) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time1) Asynchronous READY hold time1) max. 40 - - 4 4 10 + tA - - - - - 0 + 2tA + min. 2TCL TCL - 6 TCL - 10 - - 0 + tA 14 4 max. 2TCL - - 4 4 10 + tA - - ns ns ns ns ns ns ns ns ns ns ns ns t29 t30 t31 t32 t33 t34 CC 40 CC 14 CC 10 CC - CC - CC 0 + tA t35 SR 14 t36 SR 4 t37 SR 54 t58 SR 14 t59 SR 4 2TCL + t58 - 14 4 0 - - TCL - 20 + 2tA + tC + tF2) Async. READY hold time t60 SR 0 after RD, WR high (Demultiplexed Bus)2) 1) 2) tC + tF2) These timings are given for test purposes only, in order to assure recognition at a specific clock edge. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. The maximum limit for t60 must be fulfilled if the next following bus cycle is READY controlled. Data Sheet 79 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Running Cycle 1) READY Waitstate MUX/Tristate 6) t32 t33 t30 CLKOUT t29 t31 t34 ALE 7) Command RD, WR 2) t36 t35 Sync READY 3) t36 t35 3) t59 t58 Async READY 3) t59 t58 3) t60 4) t37 5) see 6) MCT04447 Figure 24 CLKOUT and READY Notes 1) Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). 2) The leading edge of the respective command depends on RW-delay. 3) READY sampled HIGH at this sampling point generates a READY controlled waitstate, READY sampled LOW at this sampling point terminates the currently running bus cycle. 4) READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). 5) If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed, if READY is removed in reponse to the command (see Note4)). 6) Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7) The next external bus cycle may start here. Data Sheet 80 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L AC Characteristics External Bus Arbitration (Operating Conditions apply) Parameter Symbol Max. CPU Clock Variable CPU Clock Unit = 25 MHz 1 / 2TCL = 1 to 25 MHz min. HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive max. - 20 20 20 24 20 24 min. 20 - - - -4 - -4 max. - 20 20 20 24 20 24 ns ns ns ns ns ns ns 20 t61 SR t62 CC - t63 CC - t64 t65 t66 t67 CC CC CC CC - -4 - -4 Data Sheet 81 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L CLKOUT t61 HOLD t63 HLDA see1) t62 BREQ 2) t64 CSx (On P6.x) 3) t66 Other Signals 1) MCT04448 Figure 25 External Bus Arbitration, Releasing the Bus Notes 1) The C161CS/JC/JI will complete the currently running bus cycle before granting bus access. 2) This is the first possibility for BREQ to get active. 3) The CS outputs will be resistive high (pullup) after t64. Data Sheet 82 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L CLKOUT 2) t61 HOLD t62 HLDA t62 BREQ 1) t62 t63 t65 CSx (On P6.x) t67 Other Signals MCT04449 Figure 26 External Bus Arbitration, (Regaining the Bus) Notes 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the C161CS/JC/JI requesting the bus. 2) The next C161CS/JC/JI driven bus cycle may start here. Data Sheet 83 V3.0, 2001-01 C161CS/JC/JI-32R C161CS/JC/JI-L Package Outline P-TQFP-128-2 (Plastic Thin Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Data Sheet 84 Dimensions in mm V3.0, 2001-01 GPP09028 Infineon goes for Business Excellence "Business excellence means intelligent approaches and clearly defined processes, which are both constantly under review and ultimately lead to good operating results. Better operating results and business excellence mean less idleness and wastefulness for all of us, more professional success, more accurate information, a better overview and, thereby, less frustration and more satisfaction." Dr. Ulrich Schumacher http://www.infineon.com Published by Infineon Technologies AG |
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